6 6 6 65 5 5 5$ $ $ $0 0 0 0 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 copyright ?2000 alliance semiconductor. all rights reserved. ? $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 4 4 4 4 4198 9 # wr #619 9 #589 .e 49# ,qwhoolzdww? # orz # srzhu # &026 # 65$0 # zlwk # wzr # &kls # (qdeohv 4198 9 # wr #619 9 #589 .e 49# ,qwhoolzdww? # orz # srzhu # &026 # 65$0 # zlwk # wzr # &kls # (qdeohv 4198 9 # wr #619 9 #589 .e 49# ,qwhoolzdww? # orz # srzhu # &026 # 65$0 # zlwk # wzr # &kls # (qdeohv 4198 9 # wr #619 9 #589 .e 49# ,qwhoolzdww? # orz # srzhu # &026 # 65$0 # zlwk # wzr # &kls # (qdeohv )hdwxuhv ? as6ua25617 ? intelliwatt? active power circuitry ? industrial temperature: -40 c to 85 c ? organization: 262,144 words 16 bits ? 2.7v to 3.6v at 55 ns ? 2.3v to 2.7v at 70 ns ? 1.65v to 2.3v at 100 ns ?cs1 and cs2 for chip selection ? low power consumption: active - 54 mw at 3.6v and 55 ns - 27 mw at 2.7v and 70 ns - 14 mw at 2.3 v and 100 ns ? low power consumption: standby - 29 w max at 3.6v -11 m w max at 2.7v -9 m w max at 2.3v ? 1.2v data retention ? equal access and cycle times ? easy memory expansion with cs , oe inputs ? smallest footprint package - 44-pin tsop ii -48-ball fbga ? esd protection 3 2000 volts ? latch-up current 3 200 ma /rjlf # eorfn # gldjudp 1024 256 16 array (4,194,304) oe cs1 we column decoder row decoder a0 a1 a2 a3 a4 a6 a7 a8 v dd v ss a12 a5 a9 a10 a11 a14 a15 a16 a17 a13 control circuit i/o0Ci/o7 i/o8Ci/o15 ub lb i/o buffer cs2 3lq # duudqjhphqw #+ wrs # ylhz , 48-csp ball-grid-array package 123456 alb oe a 0 a 1 a 2 cs2 bi/o 8 ub a 3 a 4 cs1 i/o 0 ci/o 9 i/o 10 a 5 a 6 i/o 1 i/o 2 dv ss i/o 11 a 17 a 7 i/o 3 v cc ev cc i/o 12 nc a 16 i/o 4 v ss fi/o 14 i/o 13 a 14 a 15 i/o 5 i/o 6 gi/o 15 nc a 12 a 13 we i/o 7 hnca 8 a 9 a 10 a 11 nc 6hohfwlrq # jxlgh product v cc range speed (ns) power dissipation (industrial) min (v) ty p 2 (v) max (v) operating (i cc )standby (i sb2 ) max (ma) max ( m a) as6ua25617 2.7 3.0 3.6 55 15 8 as6ua25617 2.3 2.5 2.7 70 10 4 as6ua25617 * * advance information. 1.65 2.0 2.3 100 7 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 i/o13 i/o12 v ss v cc i/o11 i/o10 i/o9 i/o8 cs2 a14 a13 a1 2 a11 a10 a4 cs i/o0 i/o1 i/o2 i/o3 v cc v ss i/o4 i/o5 i/o6 i/o7 we a5 a6 a7 tsop ii 21 22 a8 a9 ub l b i/o15 i/o14 2 a1 3 a2 4 a3 1 a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a16 a15 oe a17
6 6 6 65 5 5 5$ $ $ $0 0 0 0 ? 5 5 5 5 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 )xqfwlrqdo # ghvfulswlrq the as6ua25617 is a low-power cmos 4,194,304-bit static random access memory (sram) device organized as 262,144 words 16 bits. it is designed for memory applications where slow data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 55/70/100 ns are ideal for low-power applications. active high and low chip enables (cs1 and cs2) permit easy memory expansion with multiple-bank memory systems. when cs1 is high, or ub and lb are high or cs2 is low, the device enters standby mode: the as6ua25617 is guaranteed not to exceed 28 m w power consumption at 3.6v and 5 5ns; 100 m w at 2.7v and 70 ns; or 60 m w at 2.3v and 100 ns. the device also returns data when v cc is reduced to 1.5v for even lower power consumption. a write cycle is accomplished by asserting write enable (we ) and chip enable (cs1 ) low, ub and/or lb low, and cs2 high. data on the input pins i/o0-i/o15 is written on the rising edge of we (write cycle 1) or cs1 , cs2 (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ), chip enable (cs1 ) low, ub and/or lb low, with write enable (we ) and cs2 high. the chip drives i/o pins with the data word referenced by the input address. when either chip enable or output enable is i nactive, or write enable is active, or (ub ) and (lb ), output drivers stay in high-impedance mode. this device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be w ritten and read. lb controls the lower bits, i/o0Ci/o7, and ub controls the higher bits, i/o8Ci/o15. all chip inputs and outputs are cmos-compatible, and operation is from either a single 1.65v to 3.6v supply. device is availabl e in the jedec standard 48-ball fbga and the 44-pin tsopii packages. $evroxwh # pd[lpxp # udwlqjv stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute max- imum rating conditions for extended periods may affect reliability. 7uxwk # wdeoh key: x = dont care, l = low, h = high parameter device symbol min max unit vo l t ag e o n v cc relative to v ss v tin C0.5 v cc + 0.5 v voltage on any i/o pin relative to gnd v ti/o C0.5 v power dissipation p d C1.0w storage temperature (plastic) t stg C65 +150 o c temperature with v cc applied t bias C55 +125 o c dc output current (low) i out C20ma cs1 cs2 oe we lb ub i/o 1-8 i/o 9-16 mode power h x x x x x high-z high-z deselected standby x l x x x x high-z high-z deselected standby x x x x h h high-z high-z deselected standby l h h h l x high-z high-z output disabled active l h h h x l high-z high-z output disabled active lhlhlhd out high-z lower byte read active lhlhhlhigh-zd out upper byte read active lhlhl ld out d out word read active lhxl lh d in high-z lower byte write active lhxlhlhigh-z d in upper byte write active lhxl l l d in d in word write active
6 6 6 65 5 5 5$ $ $ $0 0 0 0 ? $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 6 6 6 6 6 6 6 65 5 5 5$ $ $ $0 0 0 0 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 5hfrpphqghg # rshudwlqj # frqglwlrq #+ ryhu # wkh # rshudwlqj # udqjh ,# &dsdflwdqfh #+ i # #4# 0+] /# 7 d # # 5rrp # whpshudwxuh /# 9 && # # 120,1$/ , 2 # parameter description test conditions min max unit v oh output high voltage i oh = 2.1ma v cc = 2.7v 2.4 v i oh = 1.5ma v cc = 2.3v 2.0 i oh = 1.65ma v cc = 1.65v 1.5 v ol output low voltage i ol = 2.1ma v cc = 2.7v 0.4 v i ol = 0.5ma v cc = 2.3v 0.4 i ol = 0.1ma v cc = 1.65v 0.2 v ih input high voltage v cc = 2.7v 2.2 v cc + 0.5 v v cc = 2.3v 2.0 v cc + 0.3 v cc = 1.65v 1.4 v cc + 0.3 v il input low voltage v cc = 2.7v -0.5 0.8 v v cc = 2.3v -0.3 0.6 v cc = 1.65v -0.3 0.4 i ix input load current gnd < v in < v cc -1 +1 m a i oz output load current gnd < v o < v cc ; outputs high z -1 +1 m a i cc v cc operating supply current i out = 0ma v cc = 3.6v 15 ma f = 1 mhz v cc = 2.7v 10 v in = cmos v cc = 2.3v 7 i cc @ 1 mhz v cc operating supply current at 1 mhz i out = 0ma v cc = 3.6v 2 ma f = 1 mhz v cc = 2.7v 1 v in = cmos v cc = 2.3v 1 i sb1 chip enable(s) power down current; ttl inputs cs1 > v ih cs2 < v il , or ub = lb > v ih v in > v ih, or v in < v il v cc = 3.6v 100 m a v cc = 2.7v v cc = 2.3v i sb2 chip enable(s) power down current; cmos inputs cs1 > v cc - 0.1v cs2 < + 0.1v, or ub = lb > v cc - 0.1v v in > v cc - 0.1v or v in < 0.3v, f = 0 v cc = 3.6v 8 m a v cc = 2.7v 4 v cc = 2.3v 4 i sbdr data retention cs1 > v cc - 0.1v cs2 < + 0.1v, or ub = lb = v cc - 0.1v v in > v cc - 0.1v or v in < 0.1v, f = 0 v cc = 1.2v 2 m a parameter symbol signals test conditions max unit input capacitance c in a, cs1 , cs2, we , oe , lb , ub v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
6 6 6 65 5 5 5$ $ $ $0 0 0 0 ? 7 7 7 7 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 5hdg # f\foh #+ ryhu # wkh # rshudwlqj # udqjh , 3,9 shaded areas indicate preliminary information. .h\ # wr # vzlwfklqj # zdyhirupv # 5hdg # zdyhirup #4#+ dgguhvv # frqwuroohg , 3,6,7,9 ## 5hdg # zdyhirup #5#+ &kls # hqdeohv /# 2( /# 8% /# /% # frqwuroohg , 3,6,8,9 # parameter symbol -55 -70 -100 unit notes min max min max min max read cycle time t rc 55 C 70 C 100 C ns address access time t aa C 55 C 70 C 100 ns 3 chip enables access time t acs1,2 C 55 C 70 C 100 ns 3 output enable (oe ) access time t oe C 25 C 35 C 50 ns output hold from address change t oh 10 C 10 C 15 C ns 5 chip enables low to output in low z t clz 10 C 10 C 10 C ns 4, 5 chip enables high to output in high z t chz 0 10 0 10 0 10 ns 4, 5 oe low to output in low z t olz 10 C 10 C 10 C ns 4, 5 ub /lb access time t ba C 55 C 70 C 100 ns ub /lb low to low z t blz 10 C 10 C 10 C ns 4, 5 ub /lb high to high z t bhz 0 10 C 10 C 10 ns 4, 5 oe high to output in high z t ohz 0 10 C 10 C 10 ns 4, 5 power up time t pu 0C0C0Cns4, 5 power down time t pd C 55 C 70 C 100 ns 4, 5 undefined/dont care falling input rising input t oh t aa t rc t oh d out address data valid previous data valid cs1 data valid t rc t aa t blz t ba t bhz address oe cs2 lb , ub d out t olz t oe t oh t acs1 t olz t oe t oh t acs1 t ohz t ohz
6 6 6 65 5 5 5$ $ $ $0 0 0 0 ? $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 8 8 8 8 6 6 6 65 5 5 5$ $ $ $0 0 0 0 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 :ulwh # f\foh #+ ryhu # wkh # rshudwlqj # udqjh , 11 shaded areas indicate preliminary information. :ulwh # zdyhirup #4#+ :( # frqwuroohg , 10,11 ## :ulwh # zdyhirup #5#+ &kls # hqdeohv # frqwuroohg , 10,11 ## parameter symbol 55 70 100 unit notes min max min max min max write cycle time t wc 55 C 70 C 100 C ns chip enable to write end t cw 40 C 60 C 80 C ns 12 address setup to write end t aw 40 C 60 C 80 C ns address setup time t as 0C0C0Cns12 write pulse width t wp 35 C 55 C 70 C ns address hold from end of write t ah 0C0C0Cns data valid to write end t dw 25 C 30 C 40 C ns data hold time t dh 0C0C0Cns4, 5 write enable to output in high z t wz 020020020ns4, 5 output active from write end t ow 5C5C5Cns4, 5 ub /lb low to end of write t bw 35 C 55 C 70 C ns address cs1 lb , ub we d in d out t wc t cw t bw t aw t as t wp t dw t dh t ow t wz t ah data undefined high z data valid cs2 t cw t ah address cs1 lb , ub we d in t wc t bw t wp t dw t dh t ow t wz d out data undefined high z high z data valid t clz cs2 t cw t ah t as t aw t cw t ah t as t aw
6 6 6 65 5 5 5$ $ $ $0 0 0 0 ? 9 9 9 9 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 'dwd # uhwhqwlrq # fkdudfwhulvwlfv #+ ryhu # wkh # rshudwlqj # udqjh , 13,5 'dwd # uhwhqwlrq # zdyhirup $& # whvw # ordgv # dqg # zdyhirupv 1rwhv 1during v cc power-up, a pull-up resistor to v cc on cs1 is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions . 4t clz and t chz are specified with c l = 5pf as in figure c. transition is measured 500 mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7cs1 and oe are low and cs2 is high for read cycle. 8 address valid prior to or coincident with cs1 transition low and cs2 high. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 cs1 or we must be high or cs2 low during address transitions. either ce or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 n/a. 13 2v data retention applies to commercial temperature range operation only. 14 c=30pf, except at high z and low z parameters, where c=5pf. parameter sym test conditions min max unit v cc for data retention v dr v cc = 1.2v cs1 3 v cc C0.1v or ub = lb > v cc - 0.1v v in 3 v cc C0.1v or v in 0.1v 1.2v C v data retention current i ccd r C2 m a chip deselect to data retention time t cdr 0Cns operation recovery time t r t rc Cns parameters 3.0v 2.5v 2.0v unit r1 1105 16670 15294 ohms r2 1550 15380 11300 ohms r th 645 8000 6500 ohms v th 1.75v 1.2v 0.85v volts v cc cs1 t r t cdr data retention mode v cc v cc v dr 3 1.2v v ih v ih v dr cs2 t r t cdr v ih v ih v dr v cc r1 r2 output 30 pf including jig and scope (a) v cc r1 r2 output 5 pf all input pulses (b) 10% 90% 10% 90% gnd v cc ty p < 5 ns (c) thevenin equivalent: output r th v including jig and scope
6 6 6 65 5 5 5$ $ $ $0 0 0 0 ? $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 : : : : 6 6 6 65 5 5 5$ $ $ $0 0 0 0 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 7\slfdo # '& # dqg # $& # fkdudfwhulvwlfv # 3dfndjh # gldjudpv # dqg # glphqvlrqv supply voltage (v) 1.7 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current supply voltage (v) 0.0 0.25 0.5 0.75 1.0 normalized t aa normalized access time vs. supply voltage vs. supply voltage ambient temperature (c) -55 105 25 0.5 1.0 0.0 1.5 2.0 2.5 normalized i sb2 normalized standby current vs. ambient temperature v cc = v cc typ supply voltage (v) 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i sb normalized standby current vs. supply voltage i sb2 supply voltage (v) 0.10 0.50 1.0 1.5 normalized i cc normalized i cc vs. cycle time 2.2 2.7 3.2 3.7 v in = v cc typ t a = 25 o c 1.7 2.2 2.7 3.2 3.7 t a = 25 o c 3.0 -0.5 v in = v cc typ v cc = 3.6v t a = 25 o c 1 5 10 15 11.9 2.8 3.7 v in = v cc typ t a = 25 o c 44-pin tsop ii min (mm) max (mm) a1.2 a 1 0.05 a 2 0.95 1.05 b0.250.45 c 0.15 (typical) d 20.85 21.05 e 10.06 10.26 h e 11.56 11.96 e 0.80 (typical) l0.400.60 d h e 1234567891011121314 44 43 42 41 40 39 38 37 36 35 34 33 32 31 15 16 30 29 17 18 19 20 28 27 26 25 c l a 1 a 2 e 44-pin tsop ii 0C5 21 24 22 23 e a b
6 6 6 65 5 5 5$ $ $ $0 0 0 0 ? ; ; ; ; $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq 3uholplqdu\ # lqirupdwlrq )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 )heuxdu\ #5333 # c1 a 654321 a b c d e f g h b1 a ball #a1 ball #a1 index b c e e2 a e2 e y d minimum typical maximum aC0.75C b 6.90 7.00 7.10 b1 C 3.75 C c 10.90 11.00 11.10 c1 C 5.25 C d 0.30 0.35 0.40 eCC1.20 e1 C 0.68 C e2 0.22 0.25 0.27 yCC0.08 notes 1. bump counts: 48 (8 row x 6 column). 2. pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3. units: millimeters. 4. all tolerances are +/- 0.050 unless otherwise specified. 5. typ: typical. 6. y is coplanarity: 0.08 (max). sram die elastomer 48-ball fbga bottom view top view detail view side view e1 die die 0.3/ tm p
6 6 6 65 5 5 5$ $ $ $0 0 0 0 did 11-20011-a. copyright ?2000 alliance semiconductor corporation (alliance)'s three-point logo, our name, and intelliwatt? ar e trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this web site and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this web site. alliance does not assume any responsi- bility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, ex cept as expressly agreed to in alliance's terms and conditions of sale (available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting system s where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of all i ance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indem- nify alliance against all claims arising from such use. ? $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: $6 9 8$ 5894: ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 ',' #440533440 $ 1#525;233 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 $//,$1&( # 6(0,&21'8&725 < < < < 2ughulqj # frghv 3duw # qxpehulqj # v\vwhp speed (ns) ordering code package type operating range 55/70/100 as6ua25617-bi 48-ball fine pitch bga industrial as6uz25617-ti 44-pin tsop ii as6ua 25617 package i sram intelliwatt? prefix device number b=csp bga t=tsop ii temperature range, i=industrial: -40c to 85c
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